122 lines
6.6 KiB
HTML
122 lines
6.6 KiB
HTML
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<title>Debugging with GDB: RISC-V Features</title>
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<link href="Concept-Index.html#Concept-Index" rel="index" title="Concept Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Standard-Target-Features.html#Standard-Target-Features" rel="up" title="Standard Target Features">
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<a name="RISC_002dV-Features"></a>
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<div class="header">
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<p>
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Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="previous">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="RISC_002dV-Features-1"></a>
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<h4 class="subsection">G.5.13 RISC-V Features</h4>
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<a name="index-target-descriptions_002c-RISC_002dV-Features"></a>
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<p>The ‘<samp>org.gnu.gdb.riscv.cpu</samp>’ feature is required for RISC-V
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targets. It should contain the registers ‘<samp>x0</samp>’ through
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‘<samp>x31</samp>’, and ‘<samp>pc</samp>’. Either the architectural names (‘<samp>x0</samp>’,
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‘<samp>x1</samp>’, etc) can be used, or the ABI names (‘<samp>zero</samp>’, ‘<samp>ra</samp>’,
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etc).
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.fpu</samp>’ feature is optional. If present, it
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should contain registers ‘<samp>f0</samp>’ through ‘<samp>f31</samp>’, ‘<samp>fflags</samp>’,
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‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’. As with the cpu feature, either the
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architectural register names, or the ABI names can be used.
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.virtual</samp>’ feature is optional. If present,
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it should contain registers that are not backed by real registers on
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the target, but are instead virtual, where the register value is
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derived from other target state. In many ways these are like
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<small>GDB</small>s pseudo-registers, except implemented by the target.
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Currently the only register expected in this set is the one byte
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‘<samp>priv</samp>’ register that contains the target’s privilege level in the
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least significant two bits.
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.csr</samp>’ feature is optional. If present, it
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should contain all of the target’s standard CSRs. Standard CSRs are
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those defined in the RISC-V specification documents. There is some
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overlap between this feature and the fpu feature; the ‘<samp>fflags</samp>’,
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‘<samp>frm</samp>’, and ‘<samp>fcsr</samp>’ registers could be in either feature. The
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expectation is that these registers will be in the fpu feature if the
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target has floating point hardware, but can be moved into the csr
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feature if the target has the floating point control registers, but no
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other floating point hardware.
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</p>
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<p>The ‘<samp>org.gnu.gdb.riscv.vector</samp>’ feature is optional. If present,
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it should contain registers ‘<samp>v0</samp>’ through ‘<samp>v31</samp>’, all of which
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must be the same size. These requirements are based on the v0.10
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draft vector extension, as the vector extension is not yet final. In
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the event that the register set of the vector extension changes for
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the final specification, the requirements given here could change for
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future releases of <small>GDB</small>.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="RX-Features.html#RX-Features" accesskey="n" rel="next">RX Features</a>, Previous: <a href="PowerPC-Features.html#PowerPC-Features" accesskey="p" rel="previous">PowerPC Features</a>, Up: <a href="Standard-Target-Features.html#Standard-Target-Features" accesskey="u" rel="up">Standard Target Features</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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