97 lines
4.0 KiB
HTML
97 lines
4.0 KiB
HTML
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<title>Using as: i386-ISA</title>
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<link href="AS-Index.html#AS-Index" rel="index" title="AS Index">
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="i386_002dDependent.html#i386_002dDependent" rel="up" title="i386-Dependent">
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<body lang="en" bgcolor="#FFFFFF" text="#000000" link="#0000FF" vlink="#800080" alink="#FF0000">
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<a name="i386_002dISA"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dBugs.html#i386_002dBugs" accesskey="n" rel="next">i386-Bugs</a>, Previous: <a href="i386_002dArch.html#i386_002dArch" accesskey="p" rel="previous">i386-Arch</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="AMD64-ISA-vs_002e-Intel64-ISA"></a>
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<h4 class="subsection">9.16.16 AMD64 ISA vs. Intel64 ISA</h4>
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<p>There are some discrepancies between AMD64 and Intel64 ISAs.
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</p>
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<ul>
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<li> For ‘<samp>movsxd</samp>’ with 16-bit destination register, AMD64
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supports 32-bit source operand and Intel64 supports 16-bit source
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operand.
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</li><li> For far branches (with explicit memory operand), both ISAs support
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32- and 16-bit operand size. Intel64 additionally supports 64-bit
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operand size, encoded as ‘<samp>ljmpq</samp>’ and ‘<samp>lcallq</samp>’ in AT&T syntax
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and with an explicit ‘<samp>tbyte ptr</samp>’ operand size specifier in Intel
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syntax.
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</li><li> ‘<samp>lfs</samp>’, ‘<samp>lgs</samp>’, and ‘<samp>lss</samp>’ similarly allow for 16-
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and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
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while Intel64 additionally supports 64-bit operand sise (80-bit memory
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operands).
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</li></ul>
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</body>
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