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673 lines
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<title>Using as: i386-Options</title>
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<a name="i386_002dOptions"></a>
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<div class="header">
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<p>
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Next: <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Options-11"></a>
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<h4 class="subsection">9.16.1 Options</h4>
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<a name="index-options-for-i386"></a>
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<a name="index-options-for-x86_002d64"></a>
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<a name="index-i386-options"></a>
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<a name="index-x86_002d64-options"></a>
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<p>The i386 version of <code>as</code> has a few machine
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dependent options:
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</p>
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<dl compact="compact">
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<dd><a name="index-_002d_002d32-option_002c-i386"></a>
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<a name="index-_002d_002d32-option_002c-x86_002d64"></a>
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<a name="index-_002d_002dx32-option_002c-i386"></a>
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<a name="index-_002d_002dx32-option_002c-x86_002d64"></a>
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<a name="index-_002d_002d64-option_002c-i386"></a>
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<a name="index-_002d_002d64-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>--32 | --x32 | --64</code></dt>
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<dd><p>Select the word size, either 32 bits or 64 bits. ‘<samp>--32</samp>’
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implies Intel i386 architecture, while ‘<samp>--x32</samp>’ and ‘<samp>--64</samp>’
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imply AMD x86-64 architecture with 32-bit or 64-bit word-size
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respectively.
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</p>
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<p>These options are only available with the ELF object file format, and
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require that the necessary BFD support has been included (on a 32-bit
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platform you have to add –enable-64-bit-bfd to configure enable 64-bit
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usage and use x86-64 as target platform).
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</p>
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</dd>
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<dt><code>-n</code></dt>
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<dd><p>By default, x86 GAS replaces multiple nop instructions used for
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alignment within code sections with multi-byte nop instructions such
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as leal 0(%esi,1),%esi. This switch disables the optimization if a single
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byte nop (0x90) is explicitly specified as the fill byte for alignment.
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</p>
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<a name="index-_002d_002ddivide-option_002c-i386"></a>
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</dd>
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<dt><code>--divide</code></dt>
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<dd><p>On SVR4-derived platforms, the character ‘<samp>/</samp>’ is treated as a comment
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character, which means that it cannot be used in expressions. The
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‘<samp>--divide</samp>’ option turns ‘<samp>/</samp>’ into a normal character. This does
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not disable ‘<samp>/</samp>’ at the beginning of a line starting a comment, or
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affect using ‘<samp>#</samp>’ for starting a comment.
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</p>
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<a name="index-_002dmarch_003d-option_002c-i386"></a>
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<a name="index-_002dmarch_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-march=<var>CPU</var>[+<var>EXTENSION</var>…]</code></dt>
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<dd><p>This option specifies the target processor. The assembler will
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issue an error message if an attempt is made to assemble an instruction
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which will not execute on the target processor. The following
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processor names are recognized:
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<code>i8086</code>,
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<code>i186</code>,
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<code>i286</code>,
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<code>i386</code>,
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<code>i486</code>,
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<code>i586</code>,
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<code>i686</code>,
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<code>pentium</code>,
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<code>pentiumpro</code>,
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<code>pentiumii</code>,
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<code>pentiumiii</code>,
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<code>pentium4</code>,
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<code>prescott</code>,
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<code>nocona</code>,
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<code>core</code>,
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<code>core2</code>,
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<code>corei7</code>,
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<code>l1om</code>,
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<code>k1om</code>,
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<code>iamcu</code>,
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<code>k6</code>,
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<code>k6_2</code>,
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<code>athlon</code>,
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<code>opteron</code>,
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<code>k8</code>,
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<code>amdfam10</code>,
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<code>bdver1</code>,
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<code>bdver2</code>,
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<code>bdver3</code>,
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<code>bdver4</code>,
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<code>znver1</code>,
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<code>znver2</code>,
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<code>znver3</code>,
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<code>btver1</code>,
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<code>btver2</code>,
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<code>generic32</code> and
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<code>generic64</code>.
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</p>
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<p>In addition to the basic instruction set, the assembler can be told to
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accept various extension mnemonics. For example,
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<code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and
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<var>vmx</var>. The following extensions are currently supported:
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<code>8087</code>,
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<code>287</code>,
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<code>387</code>,
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<code>687</code>,
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<code>no87</code>,
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<code>no287</code>,
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<code>no387</code>,
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<code>no687</code>,
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<code>cmov</code>,
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<code>nocmov</code>,
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<code>fxsr</code>,
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<code>nofxsr</code>,
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<code>mmx</code>,
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<code>nommx</code>,
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<code>sse</code>,
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<code>sse2</code>,
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<code>sse3</code>,
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<code>sse4a</code>,
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<code>ssse3</code>,
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<code>sse4.1</code>,
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<code>sse4.2</code>,
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<code>sse4</code>,
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<code>nosse</code>,
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<code>nosse2</code>,
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<code>nosse3</code>,
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<code>nosse4a</code>,
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<code>nossse3</code>,
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<code>nosse4.1</code>,
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<code>nosse4.2</code>,
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<code>nosse4</code>,
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<code>avx</code>,
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<code>avx2</code>,
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<code>noavx</code>,
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<code>noavx2</code>,
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<code>adx</code>,
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<code>rdseed</code>,
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<code>prfchw</code>,
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<code>smap</code>,
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<code>mpx</code>,
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<code>sha</code>,
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<code>rdpid</code>,
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<code>ptwrite</code>,
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<code>cet</code>,
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<code>gfni</code>,
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<code>vaes</code>,
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<code>vpclmulqdq</code>,
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<code>prefetchwt1</code>,
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<code>clflushopt</code>,
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<code>se1</code>,
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<code>clwb</code>,
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<code>movdiri</code>,
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<code>movdir64b</code>,
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<code>enqcmd</code>,
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<code>serialize</code>,
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<code>tsxldtrk</code>,
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<code>kl</code>,
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<code>nokl</code>,
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<code>widekl</code>,
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<code>nowidekl</code>,
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<code>hreset</code>,
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<code>avx512f</code>,
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<code>avx512cd</code>,
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<code>avx512er</code>,
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<code>avx512pf</code>,
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<code>avx512vl</code>,
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<code>avx512bw</code>,
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<code>avx512dq</code>,
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<code>avx512ifma</code>,
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<code>avx512vbmi</code>,
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<code>avx512_4fmaps</code>,
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<code>avx512_4vnniw</code>,
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<code>avx512_vpopcntdq</code>,
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<code>avx512_vbmi2</code>,
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<code>avx512_vnni</code>,
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<code>avx512_bitalg</code>,
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<code>avx512_vp2intersect</code>,
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<code>tdx</code>,
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<code>avx512_bf16</code>,
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<code>avx_vnni</code>,
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<code>noavx512f</code>,
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<code>noavx512cd</code>,
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<code>noavx512er</code>,
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<code>noavx512pf</code>,
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<code>noavx512vl</code>,
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<code>noavx512bw</code>,
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<code>noavx512dq</code>,
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<code>noavx512ifma</code>,
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<code>noavx512vbmi</code>,
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<code>noavx512_4fmaps</code>,
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<code>noavx512_4vnniw</code>,
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<code>noavx512_vpopcntdq</code>,
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<code>noavx512_vbmi2</code>,
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<code>noavx512_vnni</code>,
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<code>noavx512_bitalg</code>,
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<code>noavx512_vp2intersect</code>,
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<code>notdx</code>,
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<code>noavx512_bf16</code>,
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<code>noavx_vnni</code>,
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<code>noenqcmd</code>,
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<code>noserialize</code>,
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<code>notsxldtrk</code>,
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<code>amx_int8</code>,
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<code>noamx_int8</code>,
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<code>amx_bf16</code>,
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<code>noamx_bf16</code>,
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<code>amx_tile</code>,
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<code>noamx_tile</code>,
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<code>nouintr</code>,
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<code>nohreset</code>,
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<code>vmx</code>,
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<code>vmfunc</code>,
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<code>smx</code>,
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<code>xsave</code>,
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<code>xsaveopt</code>,
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<code>xsavec</code>,
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<code>xsaves</code>,
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<code>aes</code>,
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<code>pclmul</code>,
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<code>fsgsbase</code>,
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<code>rdrnd</code>,
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<code>f16c</code>,
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<code>bmi2</code>,
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<code>fma</code>,
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<code>movbe</code>,
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<code>ept</code>,
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<code>lzcnt</code>,
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<code>popcnt</code>,
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<code>hle</code>,
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<code>rtm</code>,
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<code>invpcid</code>,
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<code>clflush</code>,
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<code>mwaitx</code>,
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<code>clzero</code>,
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<code>wbnoinvd</code>,
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<code>pconfig</code>,
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<code>waitpkg</code>,
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<code>uintr</code>,
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<code>cldemote</code>,
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<code>rdpru</code>,
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<code>mcommit</code>,
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<code>sev_es</code>,
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<code>lwp</code>,
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<code>fma4</code>,
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<code>xop</code>,
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<code>cx16</code>,
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<code>syscall</code>,
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<code>rdtscp</code>,
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<code>3dnow</code>,
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<code>3dnowa</code>,
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<code>sse4a</code>,
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<code>sse5</code>,
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<code>snp</code>,
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<code>invlpgb</code>,
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<code>tlbsync</code>,
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<code>svme</code> and
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<code>padlock</code>.
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Note that rather than extending a basic instruction set, the extension
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mnemonics starting with <code>no</code> revoke the respective functionality.
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</p>
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<p>When the <code>.arch</code> directive is used with <samp>-march</samp>, the
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<code>.arch</code> directive will take precedent.
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</p>
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<a name="index-_002dmtune_003d-option_002c-i386"></a>
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<a name="index-_002dmtune_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-mtune=<var>CPU</var></code></dt>
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<dd><p>This option specifies a processor to optimize for. When used in
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conjunction with the <samp>-march</samp> option, only instructions
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of the processor specified by the <samp>-march</samp> option will be
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generated.
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</p>
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<p>Valid <var>CPU</var> values are identical to the processor list of
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<samp>-march=<var>CPU</var></samp>.
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</p>
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<a name="index-_002dmsse2avx-option_002c-i386"></a>
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<a name="index-_002dmsse2avx-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-msse2avx</code></dt>
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<dd><p>This option specifies that the assembler should encode SSE instructions
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with VEX prefix.
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</p>
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<a name="index-_002dmsse_002dcheck_003d-option_002c-i386"></a>
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<a name="index-_002dmsse_002dcheck_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-msse-check=<var>none</var></code></dt>
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<dt><code>-msse-check=<var>warning</var></code></dt>
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<dt><code>-msse-check=<var>error</var></code></dt>
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<dd><p>These options control if the assembler should check SSE instructions.
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<samp>-msse-check=<var>none</var></samp> will make the assembler not to check SSE
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instructions, which is the default. <samp>-msse-check=<var>warning</var></samp>
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will make the assembler issue a warning for any SSE instruction.
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<samp>-msse-check=<var>error</var></samp> will make the assembler issue an error
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for any SSE instruction.
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</p>
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<a name="index-_002dmavxscalar_003d-option_002c-i386"></a>
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<a name="index-_002dmavxscalar_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-mavxscalar=<var>128</var></code></dt>
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<dt><code>-mavxscalar=<var>256</var></code></dt>
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<dd><p>These options control how the assembler should encode scalar AVX
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instructions. <samp>-mavxscalar=<var>128</var></samp> will encode scalar
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AVX instructions with 128bit vector length, which is the default.
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<samp>-mavxscalar=<var>256</var></samp> will encode scalar AVX instructions
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with 256bit vector length.
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</p>
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<p>WARNING: Don’t use this for production code - due to CPU errata the
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resulting code may not work on certain models.
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</p>
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<a name="index-_002dmvexwig_003d-option_002c-i386"></a>
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<a name="index-_002dmvexwig_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-mvexwig=<var>0</var></code></dt>
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<dt><code>-mvexwig=<var>1</var></code></dt>
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<dd><p>These options control how the assembler should encode VEX.W-ignored (WIG)
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VEX instructions. <samp>-mvexwig=<var>0</var></samp> will encode WIG VEX
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instructions with vex.w = 0, which is the default.
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<samp>-mvexwig=<var>1</var></samp> will encode WIG EVEX instructions with
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vex.w = 1.
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</p>
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<p>WARNING: Don’t use this for production code - due to CPU errata the
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resulting code may not work on certain models.
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</p>
|
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<a name="index-_002dmevexlig_003d-option_002c-i386"></a>
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<a name="index-_002dmevexlig_003d-option_002c-x86_002d64"></a>
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</dd>
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<dt><code>-mevexlig=<var>128</var></code></dt>
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<dt><code>-mevexlig=<var>256</var></code></dt>
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<dt><code>-mevexlig=<var>512</var></code></dt>
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<dd><p>These options control how the assembler should encode length-ignored
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(LIG) EVEX instructions. <samp>-mevexlig=<var>128</var></samp> will encode LIG
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EVEX instructions with 128bit vector length, which is the default.
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<samp>-mevexlig=<var>256</var></samp> and <samp>-mevexlig=<var>512</var></samp> will
|
|
encode LIG EVEX instructions with 256bit and 512bit vector length,
|
|
respectively.
|
|
</p>
|
|
<a name="index-_002dmevexwig_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmevexwig_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mevexwig=<var>0</var></code></dt>
|
|
<dt><code>-mevexwig=<var>1</var></code></dt>
|
|
<dd><p>These options control how the assembler should encode w-ignored (WIG)
|
|
EVEX instructions. <samp>-mevexwig=<var>0</var></samp> will encode WIG
|
|
EVEX instructions with evex.w = 0, which is the default.
|
|
<samp>-mevexwig=<var>1</var></samp> will encode WIG EVEX instructions with
|
|
evex.w = 1.
|
|
</p>
|
|
<a name="index-_002dmmnemonic_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmmnemonic_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mmnemonic=<var>att</var></code></dt>
|
|
<dt><code>-mmnemonic=<var>intel</var></code></dt>
|
|
<dd><p>This option specifies instruction mnemonic for matching instructions.
|
|
The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will
|
|
take precedent.
|
|
</p>
|
|
<a name="index-_002dmsyntax_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmsyntax_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-msyntax=<var>att</var></code></dt>
|
|
<dt><code>-msyntax=<var>intel</var></code></dt>
|
|
<dd><p>This option specifies instruction syntax when processing instructions.
|
|
The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will
|
|
take precedent.
|
|
</p>
|
|
<a name="index-_002dmnaked_002dreg-option_002c-i386"></a>
|
|
<a name="index-_002dmnaked_002dreg-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mnaked-reg</code></dt>
|
|
<dd><p>This option specifies that registers don’t require a ‘<samp>%</samp>’ prefix.
|
|
The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent.
|
|
</p>
|
|
<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-i386"></a>
|
|
<a name="index-_002dmadd_002dbnd_002dprefix-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-madd-bnd-prefix</code></dt>
|
|
<dd><p>This option forces the assembler to add BND prefix to all branches, even
|
|
if such prefix was not explicitly specified in the source code.
|
|
</p>
|
|
<a name="index-_002dmshared-option_002c-i386"></a>
|
|
<a name="index-_002dmshared-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mno-shared</code></dt>
|
|
<dd><p>On ELF target, the assembler normally optimizes out non-PLT relocations
|
|
against defined non-weak global branch targets with default visibility.
|
|
The ‘<samp>-mshared</samp>’ option tells the assembler to generate code which
|
|
may go into a shared library where all non-weak global branch targets
|
|
with default visibility can be preempted. The resulting code is
|
|
slightly bigger. This option only affects the handling of branch
|
|
instructions.
|
|
</p>
|
|
<a name="index-_002dmbig_002dobj-option_002c-i386"></a>
|
|
<a name="index-_002dmbig_002dobj-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mbig-obj</code></dt>
|
|
<dd><p>On PE/COFF target this option forces the use of big object file
|
|
format, which allows more than 32768 sections.
|
|
</p>
|
|
<a name="index-_002dmomit_002dlock_002dprefix_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmomit_002dlock_002dprefix_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-momit-lock-prefix=<var>no</var></code></dt>
|
|
<dt><code>-momit-lock-prefix=<var>yes</var></code></dt>
|
|
<dd><p>These options control how the assembler should encode lock prefix.
|
|
This option is intended as a workaround for processors, that fail on
|
|
lock prefix. This option can only be safely used with single-core,
|
|
single-thread computers
|
|
<samp>-momit-lock-prefix=<var>yes</var></samp> will omit all lock prefixes.
|
|
<samp>-momit-lock-prefix=<var>no</var></samp> will encode lock prefix as usual,
|
|
which is the default.
|
|
</p>
|
|
<a name="index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmfence_002das_002dlock_002dadd_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mfence-as-lock-add=<var>no</var></code></dt>
|
|
<dt><code>-mfence-as-lock-add=<var>yes</var></code></dt>
|
|
<dd><p>These options control how the assembler should encode lfence, mfence and
|
|
sfence.
|
|
<samp>-mfence-as-lock-add=<var>yes</var></samp> will encode lfence, mfence and
|
|
sfence as ‘<samp>lock addl $0x0, (%rsp)</samp>’ in 64-bit mode and
|
|
‘<samp>lock addl $0x0, (%esp)</samp>’ in 32-bit mode.
|
|
<samp>-mfence-as-lock-add=<var>no</var></samp> will encode lfence, mfence and
|
|
sfence as usual, which is the default.
|
|
</p>
|
|
<a name="index-_002dmrelax_002drelocations_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmrelax_002drelocations_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mrelax-relocations=<var>no</var></code></dt>
|
|
<dt><code>-mrelax-relocations=<var>yes</var></code></dt>
|
|
<dd><p>These options control whether the assembler should generate relax
|
|
relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
|
|
R_X86_64_REX_GOTPCRELX, in 64-bit mode.
|
|
<samp>-mrelax-relocations=<var>yes</var></samp> will generate relax relocations.
|
|
<samp>-mrelax-relocations=<var>no</var></samp> will not generate relax
|
|
relocations. The default can be controlled by a configure option
|
|
<samp>--enable-x86-relax-relocations</samp>.
|
|
</p>
|
|
<a name="index-_002dmalign_002dbranch_002dboundary_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmalign_002dbranch_002dboundary_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-malign-branch-boundary=<var>NUM</var></code></dt>
|
|
<dd><p>This option controls how the assembler should align branches with segment
|
|
prefixes or NOP. <var>NUM</var> must be a power of 2. It should be 0 or
|
|
no less than 16. Branches will be aligned within <var>NUM</var> byte
|
|
boundary. <samp>-malign-branch-boundary=0</samp>, which is the default,
|
|
doesn’t align branches.
|
|
</p>
|
|
<a name="index-_002dmalign_002dbranch_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmalign_002dbranch_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-malign-branch=<var>TYPE</var>[+<var>TYPE</var>...]</code></dt>
|
|
<dd><p>This option specifies types of branches to align. <var>TYPE</var> is
|
|
combination of ‘<samp>jcc</samp>’, which aligns conditional jumps,
|
|
‘<samp>fused</samp>’, which aligns fused conditional jumps, ‘<samp>jmp</samp>’,
|
|
which aligns unconditional jumps, ‘<samp>call</samp>’ which aligns calls,
|
|
‘<samp>ret</samp>’, which aligns rets, ‘<samp>indirect</samp>’, which aligns indirect
|
|
jumps and calls. The default is <samp>-malign-branch=jcc+fused+jmp</samp>.
|
|
</p>
|
|
<a name="index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmalign_002dbranch_002dprefix_002dsize_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-malign-branch-prefix-size=<var>NUM</var></code></dt>
|
|
<dd><p>This option specifies the maximum number of prefixes on an instruction
|
|
to align branches. <var>NUM</var> should be between 0 and 5. The default
|
|
<var>NUM</var> is 5.
|
|
</p>
|
|
<a name="index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-i386"></a>
|
|
<a name="index-_002dmbranches_002dwithin_002d32B_002dboundaries-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mbranches-within-32B-boundaries</code></dt>
|
|
<dd><p>This option aligns conditional jumps, fused conditional jumps and
|
|
unconditional jumps within 32 byte boundary with up to 5 segment prefixes
|
|
on an instruction. It is equivalent to
|
|
<samp>-malign-branch-boundary=32</samp>
|
|
<samp>-malign-branch=jcc+fused+jmp</samp>
|
|
<samp>-malign-branch-prefix-size=5</samp>.
|
|
The default doesn’t align branches.
|
|
</p>
|
|
<a name="index-_002dmlfence_002dafter_002dload_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmlfence_002dafter_002dload_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mlfence-after-load=<var>no</var></code></dt>
|
|
<dt><code>-mlfence-after-load=<var>yes</var></code></dt>
|
|
<dd><p>These options control whether the assembler should generate lfence
|
|
after load instructions. <samp>-mlfence-after-load=<var>yes</var></samp> will
|
|
generate lfence. <samp>-mlfence-after-load=<var>no</var></samp> will not generate
|
|
lfence, which is the default.
|
|
</p>
|
|
<a name="index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmlfence_002dbefore_002dindirect_002dbranch_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mlfence-before-indirect-branch=<var>none</var></code></dt>
|
|
<dt><code>-mlfence-before-indirect-branch=<var>all</var></code></dt>
|
|
<dt><code>-mlfence-before-indirect-branch=<var>register</var></code></dt>
|
|
<dt><code>-mlfence-before-indirect-branch=<var>memory</var></code></dt>
|
|
<dd><p>These options control whether the assembler should generate lfence
|
|
before indirect near branch instructions.
|
|
<samp>-mlfence-before-indirect-branch=<var>all</var></samp> will generate lfence
|
|
before indirect near branch via register and issue a warning before
|
|
indirect near branch via memory.
|
|
It also implicitly sets <samp>-mlfence-before-ret=<var>shl</var></samp> when
|
|
there’s no explicit <samp>-mlfence-before-ret=</samp>.
|
|
<samp>-mlfence-before-indirect-branch=<var>register</var></samp> will generate
|
|
lfence before indirect near branch via register.
|
|
<samp>-mlfence-before-indirect-branch=<var>memory</var></samp> will issue a
|
|
warning before indirect near branch via memory.
|
|
<samp>-mlfence-before-indirect-branch=<var>none</var></samp> will not generate
|
|
lfence nor issue warning, which is the default. Note that lfence won’t
|
|
be generated before indirect near branch via register with
|
|
<samp>-mlfence-after-load=<var>yes</var></samp> since lfence will be generated
|
|
after loading branch target register.
|
|
</p>
|
|
<a name="index-_002dmlfence_002dbefore_002dret_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmlfence_002dbefore_002dret_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mlfence-before-ret=<var>none</var></code></dt>
|
|
<dt><code>-mlfence-before-ret=<var>shl</var></code></dt>
|
|
<dt><code>-mlfence-before-ret=<var>or</var></code></dt>
|
|
<dt><code>-mlfence-before-ret=<var>yes</var></code></dt>
|
|
<dt><code>-mlfence-before-ret=<var>not</var></code></dt>
|
|
<dd><p>These options control whether the assembler should generate lfence
|
|
before ret. <samp>-mlfence-before-ret=<var>or</var></samp> will generate
|
|
generate or instruction with lfence.
|
|
<samp>-mlfence-before-ret=<var>shl/yes</var></samp> will generate shl instruction
|
|
with lfence. <samp>-mlfence-before-ret=<var>not</var></samp> will generate not
|
|
instruction with lfence. <samp>-mlfence-before-ret=<var>none</var></samp> will not
|
|
generate lfence, which is the default.
|
|
</p>
|
|
<a name="index-_002dmx86_002dused_002dnote_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmx86_002dused_002dnote_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mx86-used-note=<var>no</var></code></dt>
|
|
<dt><code>-mx86-used-note=<var>yes</var></code></dt>
|
|
<dd><p>These options control whether the assembler should generate
|
|
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
|
|
GNU property notes. The default can be controlled by the
|
|
<samp>--enable-x86-used-note</samp> configure option.
|
|
</p>
|
|
<a name="index-_002dmevexrcig_003d-option_002c-i386"></a>
|
|
<a name="index-_002dmevexrcig_003d-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mevexrcig=<var>rne</var></code></dt>
|
|
<dt><code>-mevexrcig=<var>rd</var></code></dt>
|
|
<dt><code>-mevexrcig=<var>ru</var></code></dt>
|
|
<dt><code>-mevexrcig=<var>rz</var></code></dt>
|
|
<dd><p>These options control how the assembler should encode SAE-only
|
|
EVEX instructions. <samp>-mevexrcig=<var>rne</var></samp> will encode RC bits
|
|
of EVEX instruction with 00, which is the default.
|
|
<samp>-mevexrcig=<var>rd</var></samp>, <samp>-mevexrcig=<var>ru</var></samp>
|
|
and <samp>-mevexrcig=<var>rz</var></samp> will encode SAE-only EVEX instructions
|
|
with 01, 10 and 11 RC bits, respectively.
|
|
</p>
|
|
<a name="index-_002dmamd64-option_002c-x86_002d64"></a>
|
|
<a name="index-_002dmintel64-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-mamd64</code></dt>
|
|
<dt><code>-mintel64</code></dt>
|
|
<dd><p>This option specifies that the assembler should accept only AMD64 or
|
|
Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
|
|
only and AMD64 ISAs.
|
|
</p>
|
|
<a name="index-_002dO0-option_002c-i386"></a>
|
|
<a name="index-_002dO0-option_002c-x86_002d64"></a>
|
|
<a name="index-_002dO-option_002c-i386"></a>
|
|
<a name="index-_002dO-option_002c-x86_002d64"></a>
|
|
<a name="index-_002dO1-option_002c-i386"></a>
|
|
<a name="index-_002dO1-option_002c-x86_002d64"></a>
|
|
<a name="index-_002dO2-option_002c-i386"></a>
|
|
<a name="index-_002dO2-option_002c-x86_002d64"></a>
|
|
<a name="index-_002dOs-option_002c-i386"></a>
|
|
<a name="index-_002dOs-option_002c-x86_002d64"></a>
|
|
</dd>
|
|
<dt><code>-O0 | -O | -O1 | -O2 | -Os</code></dt>
|
|
<dd><p>Optimize instruction encoding with smaller instruction size. ‘<samp>-O</samp>’
|
|
and ‘<samp>-O1</samp>’ encode 64-bit register load instructions with 64-bit
|
|
immediate as 32-bit register load instructions with 31-bit or 32-bits
|
|
immediates, encode 64-bit register clearing instructions with 32-bit
|
|
register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
|
|
register clearing instructions with 128-bit VEX vector register
|
|
clearing instructions, encode 128-bit/256-bit EVEX vector
|
|
register load/store instructions with VEX vector register load/store
|
|
instructions, and encode 128-bit/256-bit EVEX packed integer logical
|
|
instructions with 128-bit/256-bit VEX packed integer logical.
|
|
</p>
|
|
<p>‘<samp>-O2</samp>’ includes ‘<samp>-O1</samp>’ optimization plus encodes
|
|
256-bit/512-bit EVEX vector register clearing instructions with 128-bit
|
|
EVEX vector register clearing instructions. In 64-bit mode VEX encoded
|
|
instructions with commutative source operands will also have their
|
|
source operands swapped if this allows using the 2-byte VEX prefix form
|
|
instead of the 3-byte one. Certain forms of AND as well as OR with the
|
|
same (register) operand specified twice will also be changed to TEST.
|
|
</p>
|
|
<p>‘<samp>-Os</samp>’ includes ‘<samp>-O2</samp>’ optimization plus encodes 16-bit, 32-bit
|
|
and 64-bit register tests with immediate as 8-bit register test with
|
|
immediate. ‘<samp>-O0</samp>’ turns off this optimization.
|
|
</p>
|
|
</dd>
|
|
</dl>
|
|
|
|
<hr>
|
|
<div class="header">
|
|
<p>
|
|
Next: <a href="i386_002dDirectives.html#i386_002dDirectives" accesskey="n" rel="next">i386-Directives</a>, Up: <a href="i386_002dDependent.html#i386_002dDependent" accesskey="u" rel="up">i386-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
|
|
</div>
|
|
|
|
|
|
|
|
</body>
|
|
</html>
|