109 lines
3.4 KiB
ArmAsm
109 lines
3.4 KiB
ArmAsm
/*****************************************************************************
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* cpu-a.S: arm cpu detection
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*****************************************************************************
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* Copyright (C) 2009-2025 x264 project
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*
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* Authors: David Conrad <lessen42@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111, USA.
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*
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* This program is also available under a commercial proprietary license.
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* For more information, contact us at licensing@x264.com.
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*****************************************************************************/
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#include "asm.S"
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.align 2
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// done in gas because .fpu neon overrides the refusal to assemble
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// instructions the selected -march/-mcpu doesn't support
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function cpu_neon_test
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vadd.i16 q0, q0, q0
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bx lr
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endfunc
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// return: 0 on success
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// 1 if counters were already enabled
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// 9 if lo-res counters were already enabled
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function cpu_enable_armv7_counter, export=0
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mrc p15, 0, r2, c9, c12, 0 // read PMNC
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ands r0, r2, #1
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andne r0, r2, #9
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orr r2, r2, #1 // enable counters
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bic r2, r2, #8 // full resolution
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mcreq p15, 0, r2, c9, c12, 0 // write PMNC
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mov r2, #1 << 31 // enable cycle counter
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mcr p15, 0, r2, c9, c12, 1 // write CNTENS
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bx lr
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endfunc
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function cpu_disable_armv7_counter, export=0
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mrc p15, 0, r0, c9, c12, 0 // read PMNC
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bic r0, r0, #1 // disable counters
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mcr p15, 0, r0, c9, c12, 0 // write PMNC
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bx lr
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endfunc
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.macro READ_TIME r
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mrc p15, 0, \r, c9, c13, 0
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.endm
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// return: 0 if transfers neon -> arm transfers take more than 10 cycles
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// nonzero otherwise
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function cpu_fast_neon_mrc_test
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// check for user access to performance counters
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mrc p15, 0, r0, c9, c14, 0
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cmp r0, #0
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bxeq lr
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push {r4-r6,lr}
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bl cpu_enable_armv7_counter
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ands r1, r0, #8
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mov r3, #0
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mov ip, #4
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mov r6, #4
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moveq r5, #1
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movne r5, #64
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average_loop:
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mov r4, r5
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READ_TIME r1
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1: subs r4, r4, #1
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.rept 8
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vmov.u32 lr, d0[0]
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add lr, lr, lr
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.endr
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bgt 1b
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READ_TIME r2
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subs r6, r6, #1
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sub r2, r2, r1
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cmpgt r2, #30 << 3 // assume context switch if it took over 30 cycles
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addle r3, r3, r2
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subsle ip, ip, #1
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bgt average_loop
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// disable counters if we enabled them
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ands r0, r0, #1
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bleq cpu_disable_armv7_counter
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lsr r0, r3, #5
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cmp r0, #10
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movgt r0, #0
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pop {r4-r6,pc}
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endfunc
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